{
    "Accelerated and High-Performance Computing (FPGA / GPU)": [
        {
            "title": "GPU accelerated adaptive banded event alignment for rapid comparative nanopore signal analysis",
            "venue": "BMC Bioinformatics",
            "year": "2020",
            "abstract": "[BACKGROUND:] Nanopore sequencing enables portable, real-time sequencing applications, including point-of-care diagnostics and in-the-field genotyping. Achieving these outcomes requires efficient bioinformatic algorithms for the analysis of raw nanopore signal data. However, comparing raw nanopore signals to a biological reference sequence is a computationally complex task. The dynamic programming algorithm called Adaptive Banded Event Alignment (ABEA) is a crucial step in polishing sequencing data and identifying non-standard nucleotides, such as measuring DNA methylation. Here, we parallelise and optimise an implementation of the ABEA algorithm (termed f5c) to efficiently run on heterogeneous CPU-GPU architectures. [RESULTS:] By optimising memory, computations and load balancing between CPU and GPU, we demonstrate how f5c can perform \u00e2\u0088\u00bc3-5 \u00c3\u0097 faster than an optimised version of the original CPU-only implementation of ABEA in the Nanopolish software package. We also show that f5c enables DNA methylation detection on-the-fly using an embedded System on Chip (SoC) equipped with GPUs. [CONCLUSIONS:] Our work not only demonstrates that complex genomics analyses can be performed on lightweight computing systems, but also benefits High-Performance Computing (HPC). The associated source code for f5c along with GPU optimised ABEA is available at https://github.com/hasindu2008/f5c.",
            "authors": [
                "Hasindu Gamaarachchi",
                "Chun Wai Lam",
                "Gihan Jayatilaka",
                "Hiruna Samarakoon",
                "Jared T. Simpson",
                "Martin A. Smith",
                "Sri Parameswaran"
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            "funding": "Jared T. Simpson is supported by the Ontario Institute for Cancer Research through funds provided by the Government of Ontario and the Government of Canada through Genome Canada and Ontario Genomics (OGI-136).",
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        {
            "title": "Power-Aware High-Level Synthesis Flow for Mapping FPGA Designs",
            "venue": "2019 Moratuwa Engineering Research Conference (MERCon)",
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            "abstract": "Present Field Programmable Gate Array (FPGA) manufacturers incorporate multi-millions of logic resources which enables hardware designers to design applications extending to large scales. However, handling such applications by existing FPGA Computer Aided Design (CAD) flow requires more improvement in terms of area, performance and power efficiency considerations. The current CAD flow requires the input design to be in Register Transfer Level (RTL). RTL input designs limit the design productivity only to hardware experts in performing analysis for various optimisations. Optimising RTL designs manually are increasingly hard. High-Level Synthesis (HLS) is an approach capable of increasing the design productivity of hardware applications compared to commonly used Hardware Description Languages (HDLs) and is known to be an intelligent approach for performing optimisations at a higher level of abstraction. In this paper, an approach that follows the HLS flow to cater to the mapping of FPGA applications in a power efficient manner using a communication-aware partitioning strategy is proposed. From experiments, it was possible to achieve an average reduction of 8.39% routing thermal power and 3.34% total power using the proposed approach.",
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                "Integrated circuit interconnections",
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        {
            "title": "Accelerating string matching for bio-computing applications on multi-core CPUs",
            "venue": "2012 IEEE 7th International Conference on Industrial and Information Systems (ICIIS)",
            "year": "2012",
            "abstract": "Huge amount of data in the form of strings are being handled in bio-computing applications and searching algorithms are quite frequently used in them. Many methods utilizing on both software and hardware are being proposed to accelerate processing of such data. The typical hardware-based acceleration techniques either require special hardware such as generalpurpose graphics processing units (GPGPUs) or need building a new hardware such as an FPGA based design. On the other hard, software-based acceleration techniques are easier since they only require some changes in the software code or the software architecture. Typical software-based techniques make use of computers connected over a network, also known as a network grid to accelerate the processing. In this paper, we test the hypothesis that multi-core architectures should provide better performance in this kind of computation, but still it would depend on the algorithm selected as well as the programming model being utilized. We present the acceleration of a string-searching algorithm on a multi-core CPU via a POSIX thread based implementation. Our implementation on an 8-core processor (that supports 16-threads) resulted in 9x throughput improvement compared to a single thread implementation.",
            "authors": [
                "Damayanthi Herath",
                "Chathurika Lakmali",
                "Roshan Ragel"
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    "Computational BioEngineering": [
        {
            "title": "Non-contact Infant Sleep Apnea Detection",
            "venue": "IEEE International Conference on Industrial and Information Systems (ICIIS)",
            "year": "2019",
            "abstract": "Sleep apnea is a breathing disorder where a person repeatedly stops breathing in sleep. Early detection is crucial for infants because it might bring long term adversities. The existing accurate detection mechanism (pulse oximetry) is a skin contact measurement. The existing non-contact mechanisms (acoustics, video processing) are not accurate enough. This paper presents a novel algorithm for the detection of sleep apnea with video processing. The solution is non-contact, accurate and lightweight enough to run on a single board computer. The paper discusses the accuracy of the algorithm on real data, advantages of the new algorithm, its limitations and suggests future improvements.",
            "authors": [
                "Gihan Jayatilaka",
                "Harshana Weligampola",
                "Suren Sritharan",
                "Pankayaraj Pathmanathan",
                "Roshan Ragel",
                "Isuru Nawinne"
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        {
            "title": "Genopo: a nanopore sequencing analysis toolkit for portable Android devices",
            "venue": "Communications Biology",
            "year": "2020",
            "abstract": "The advent of portable nanopore sequencing devices has enabled DNA and RNA sequencing to be performed in the field or the clinic. However, advances in in situ genomics require parallel development of portable, offline solutions for the computational analysis of sequencing data. Here we introduce Genopo, a mobile toolkit for nanopore sequencing analysis. Genopo compacts popular bioinformatics tools to an Android application, enabling fully portable computation. To demonstrate its utility for in situ genome analysis, we use Genopo to determine the complete genome sequence of the human coronavirus SARS-CoV-2 in nine patient isolates sequenced on a nanopore device, with Genopo executing this workflow in less than 30\u00e2\u0080\u0089min per sample on a range of popular smartphones. We further show how Genopo can be used to profile DNA methylation in a human genome sample, illustrating a flexible, efficient architecture that is suitable to run many popular bioinformatics tools and accommodate small or large genomes. As the first ever smartphone application for nanopore sequencing analysis, Genopo enables the genomics community to harness this cheap, ubiquitous computational resource.",
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                "Genopo",
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            "title": "Accelerating string matching for bio-computing applications on multi-core CPUs",
            "venue": "2012 IEEE 7th International Conference on Industrial and Information Systems (ICIIS)",
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            "abstract": "Huge amount of data in the form of strings are being handled in bio-computing applications and searching algorithms are quite frequently used in them. Many methods utilizing on both software and hardware are being proposed to accelerate processing of such data. The typical hardware-based acceleration techniques either require special hardware such as generalpurpose graphics processing units (GPGPUs) or need building a new hardware such as an FPGA based design. On the other hard, software-based acceleration techniques are easier since they only require some changes in the software code or the software architecture. Typical software-based techniques make use of computers connected over a network, also known as a network grid to accelerate the processing. In this paper, we test the hypothesis that multi-core architectures should provide better performance in this kind of computation, but still it would depend on the algorithm selected as well as the programming model being utilized. We present the acceleration of a string-searching algorithm on a multi-core CPU via a POSIX thread based implementation. Our implementation on an 8-core processor (that supports 16-threads) resulted in 9x throughput improvement compared to a single thread implementation.",
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            "title": "Detection of Novel Biomarker Genes of Alzheimer\u00e2\u0080\u0099s Disease Using Gene Expression Data",
            "venue": "2020 Moratuwa Engineering Research Conference (MERCon)",
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            "abstract": "It is well recognized, that most common form of dementia is Alzheimer's disease and a successful cure or medication is not discovered. A plethora of research has been conducted to understand the underlying mechanism and the pathogenesis of the Alzheimer's disease. To explore the underlying genetic structure of the disease, gene expression data is being used by many researches and computational and statistical approaches were used to identify possible genes that are risk. In this paper, we propose a machine learning framework that can be used to identify possible bio-marker genes. Our experiments discover possible set of 14 genes, which some of them are validated by biological sources. We also present a critical analysis of the propose machine learning framework using GSE5281 gene dataset.",
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            "title": "A Data Driven Binning Method to Recover More Nucleotide Sequences of Species in a Metagenome",
            "venue": "2020 Moratuwa Engineering Research Conference (MERCon)",
            "year": "2020",
            "abstract": "Metagenomics accelerated the process of studying different species and their dynamics in multiple environments. A key step in a metagenomic study is to group nucleotide sequences belonging to an individual or closely related species which is often termed binning. Multiple machine learning techniques have been adopted in binning metagenomic sequences. Specifically, unsupervised learning is being used in most of the recent binning methods. This work considers data-driven methods for binning metagenomic sequences and discusses such approaches in detail. Furthermore, it explores on increasing the amount of metagenomic sequences binned while maintaining a reasonable binning accuracy. Consequently, a dissimilarity-based approach is proposed to improve the number of contigs binned by an existing binning method. It is shown to result in a 10% increase in the number of contigs binned compared to the original approach. Accordingly, this work suggests that the effective use of observed data which may be discarded as outliers otherwise, may result in improved performance in binning.",
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            "venue": "2020 IEEE Conference on Computational Intelligence in Bioinformatics and Computational Biology (CIBCB)",
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            "title": "Revealing MicroRNA Biomarkers for Alzheimer\u00e2\u0080\u0099s Disease Using Next Generation Sequencing Data",
            "venue": "2021 10th International Conference on Information and Automation for Sustainability (ICIAfS)",
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        {
            "title": "DeepSelectNet: deep neural network based selective sequencing for oxford nanopore sequencing",
            "venue": "BMC bioinformatics",
            "year": "2023",
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            "venue": "Sri Lanka Journal of Medicine",
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            "abstract": "Dengue outbreaks pose a significant public health challenge in tropical and subtropical regions globally, necessitating effective predictive models for early detection and intervention. This study examines the complex nature of the disease by analyzing weather parameters such as temperature, wind speed, precipitation, and humidity. Through machine learning techniques, we successfully forecasted dengue outbreaks in nine districts in Sri Lanka and identified similar weather and dengue patterns in districts such as Gampaha, Colombo, Kandy and Kurunegala. These findings are important for developing an early warning system, optimizing public health measures, and efficiently allocating resources to minimize the negative impact on communities. Furthermore, the model offers valuable insights for epidemiological research on dengue spread and control.",
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        {
            "title": "Non-contact Infant Sleep Apnea Detection",
            "venue": "IEEE International Conference on Industrial and Information Systems (ICIIS)",
            "year": "2019",
            "abstract": "Sleep apnea is a breathing disorder where a person repeatedly stops breathing in sleep. Early detection is crucial for infants because it might bring long term adversities. The existing accurate detection mechanism (pulse oximetry) is a skin contact measurement. The existing non-contact mechanisms (acoustics, video processing) are not accurate enough. This paper presents a novel algorithm for the detection of sleep apnea with video processing. The solution is non-contact, accurate and lightweight enough to run on a single board computer. The paper discusses the accuracy of the algorithm on real data, advantages of the new algorithm, its limitations and suggests future improvements.",
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            "title": "An optical physics inspired CNN approach for intrinsic image decomposition",
            "venue": "2021 IEEE International Conference on Image Processing (ICIP)",
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            "abstract": "Intrinsic Image Decomposition is an open problem of generating the constituents of an image. Generating reflectance and shading from a single image is a challenging task specifically when there is no ground truth. There is a lack of unsupervised learning approaches for decomposing an image into reflectance and shading using a single image. We propose a neural network architecture capable of this decomposition using physics-based parameters derived from the image. Through experimental results, we show that (a) the proposed methodology outperforms the existing deep learning-based IID techniques and (b) the derived parameters improve the efficacy significantly. We conclude with a closer analysis of the results (numerical and example images) showing several avenues for improvement.",
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            "title": "DeepLight: Robust & Unobtrusive Real-time Screen-Camera Communication for Real-World Displays",
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            "title": "Objectively Measure Player Performance on Olympic Weightlifting",
            "venue": "2021 10th International Conference on Information and Automation for Sustainability (ICIAfS)",
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            "abstract": "In Olympic-style weightlifting athlete attempts to lift the weight plates on a barbell and scores are determined by a combination of the successful highest weight achieved in snatch and the clean-and-jerk actions. However, the current method does not objectively measure the player techniques. In this paper, we introduce a novel method to objectively measure player performance on weightlifting using human action recognition in videos. We introduce a method to assess player techniques in weightlifting by using skeleton-based human action recognition. In order to achieve our goal, we further introduce a new video dataset for action recognition in weightlifting which is annotated to frame level and introduce an automated scoring system through action recognition. We conclude our paper with qualitative and quantitative experimental results using non-Olympic players and 2016 Gold, Silver, and Bronze medalists in different weight categories (both men and women).",
            "authors": [
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        {
            "title": "Semantic segmentation using Vision Transformers: A survey",
            "venue": "Engineering Applications of Artificial Intelligence",
            "year": "2023",
            "abstract": "Semantic segmentation has a broad range of applications in a variety of domains including land coverage analysis, autonomous driving, and medical image analysis. Convolutional neural networks (CNN) and Vision Transformers (ViTs) provide the architecture models for semantic segmentation. Even though ViTs have proven success in image classification, they cannot be directly applied to dense prediction tasks such as image segmentation and object detection since ViT is not a general purpose backbone due to its patch partitioning scheme. In this survey, we discuss some of the different ViT architectures that can be used for semantic segmentation and how their evolution managed the above-stated challenge. The rise of ViT and its performance with a high success rate motivated the community to slowly replace the traditional convolutional neural networks in various computer vision tasks. This survey aims to review and compare the performances of ViT architectures designed for semantic segmentation using benchmarking datasets. This will be worthwhile for the community to yield knowledge regarding the implementations carried out in semantic segmentation and to discover more efficient methodologies using ViTs.",
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        {
            "title": "Unified Spatio-Temporal Tri-Perspective View Representation for 3D Semantic Occupancy Prediction",
            "venue": "Machine Learning for Autonomous Driving Workshop, The 39th Annual AAAI Conference on Artificial Intelligence (AAAI-W) 2025",
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            "abstract": "Holistic understanding and reasoning in 3D scenes are crucial for the success of autonomous driving systems. The evolution of 3D semantic occupancy prediction as a pretraining task for autonomous driving and robotic applications captures finer 3D details compared to traditional 3D detection methods. Vision-based 3D semantic occupancy prediction is increasingly overlooked in favor of LiDAR-based approaches, which have shown superior performance in recent years. However, we present compelling evidence that there is still potential for enhancing vision-based methods. Existing approaches predominantly focus on spatial cues such as tri-perspective view (TPV) embeddings, often overlooking temporal cues. This study introduces S2TPVFormer, a spatiotemporal transformer architecture designed to predict temporally coherent 3D semantic occupancy. By introducing temporal cues through a novel Temporal Cross-View Hybrid Attention mechanism (TCVHA), we generate Spatiotemporal TPV (S2TPV) embeddings that enhance the prior process. Experimental evaluations on the nuScenes dataset demonstrate a significant +4.1% of absolute gain in mean Intersection over Union (mIoU) for 3D semantic occupancy compared to baseline TPVFormer, validating the effectiveness of S2TPVFormer in advancing 3D scene perception.",
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            "title": "Hardware software co-design of the Aho-Corasick algorithm: Scalable for protein identification?",
            "venue": "2013 IEEE 8th International Conference on Industrial and Information Systems",
            "year": "2013",
            "abstract": "Pattern matching is commonly required in many application areas and bioinformatics is a major area of interest that requires both exact and approximate pattern matching. Much work has been done in this area, yet there is still a significant space for improvement in efficiency, flexibility, and throughput. This paper presents a hardware software co-design of Aho-Corasick algorithm in Nios II soft-processor and a study on its scalability for a pattern matching application. A software only approach is used to compare the throughput and the scalability of the hardware software co-design approach. According to the results we obtained, we conclude that the hardware software co-design implementation shows a maximum of 10 times speed up for pattern size of 1200 peptides compared to the software only implementation. The results also show that the hardware software co-design approach scales well for increasing data size compared to the software only approach.",
            "authors": [
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                "S.D. Dewasurendra",
                "R.G. Ragel"
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            "doi": "https://doi.org/10.1109/ICIInfS.2013.6732003",
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            "title": "Hardware accelerated protein inference framework",
            "venue": "2013 IEEE 8th International Conference on Industrial and Information Systems",
            "year": "2013",
            "abstract": "Protein inference plays a vital role in the proteomics study. Two major approaches could be used to handle the problem of protein inference; top-down and bottom-up. This paper presents a framework for protein inference, which uses hardware accelerated protein inference framework for handling the most important step in a bottom-up approach, viz. peptide identification during the assembling process. In our framework, identified peptides and their probabilities are used to predict the most suitable reference protein cluster for a given input amino acid sequence with the probability of identified peptides. The framework is developed on an FPGA where hardware software co-design techniques are used to accelerate the computationally intensive parts of the protein inference process. In the paper we have measured, compared and reported the time taken for the protein inference process in our framework against a pure software implementation.",
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                "S. D. Dewasurendra",
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            "title": "A Study on Instruction-set Selection Using Multi-application Based Application Specific Instruction-set Processors",
            "venue": "2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems",
            "year": "2013",
            "abstract": "Efficiency in embedded systems is paramount to achieve high performance while consuming less area and power. Processors in embedded systems have to be designed carefully to achieve such design constraints. Application Specific Instruction set Processors (ASIPs) exploit the nature of applications to design an optimal instruction set. Despite being not general to execute any application, ASIPs are highly preferred in the embedded systems industry where the devices are produced to satisfy a certain type of application domain/s (either intra-domain or inter-domain). Typically, ASIPs are designed from a base-processor and functionalities are added for applications. This paper studies the multi-application ASIPs and their instruction sets, extensively analyzing the instructions for inter-domain and intra-domain designs. Metrics analyzed are the reusable instructions and the extra cost to add a certain application, together with the hardware synthesis numbers, such as area, timing and delay. A wide range of applications from various application benchmarks (BioPerf, CommBench, MediaBench, MiBench and SPEC2006) and domains are analyzed for three different architectures (LEON2, PISA and ARM-Thumb). Processors are generated for these architectures for different configurations to analyze and synthesize. Our study shows that the intra-domain applications contain larger number of common instructions, whereas the inter-domain applications have very less common instructions, regardless the kind of architecture (and therefore the ISA).",
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        {
            "title": "CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors",
            "venue": "2013 Design, Automation & Test in Europe Conference & Exhibition (DATE)",
            "year": "2013",
            "abstract": "Soft error has been identified as one of the major challenges to CMOS technology based computing systems. To mitigate this problem, error recovery is a key component, which usually accounts for a substantial cost, since they must introduce redundancies in either time or space. Consequently, using state-of-art recovery techniques could heavily worsen the design constraint, which is fairly stringent for embedded system design. In this paper, we propose a HW/SW methodology that generates the processor, which performs finely configured error recovery functionality targeting the given design constraints (e.g., performance, area and power). Our methodology employs three application-specific optimization heuristics, which generate the optimized composition and configuration based on the two primitive error recovery techniques. The resultant processor is composed of selected primitive techniques at corresponding instruction execution, and configured to perform error recovery at run-time accordingly to the scheme determined at design time. The experiment results have shown that our methodology can at best achieve nine times reliability while maintaining the given constraints, in comparison to the state of the art.",
            "authors": [
                "Tuo Li",
                "Muhammad Shafique",
                "Semeen Rehman",
                "Swarnalatha Radhakrishnan",
                "Roshan Ragel",
                "Jude Angelo Ambrose",
                "J\u00c3\u00b6rg Henkel",
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        {
            "title": "DRMA: dynamically reconfigurable MPSoC architecture",
            "venue": "GLSVLSI '13: Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI",
            "year": "2013",
            "abstract": "Embedded systems are ubiquitous and are deployed in a large range of applications. Designing and fabricating Integrated Circuits (ICs) targeting such different range of applications is expensive. Designers seek flexible processors which efficiently execute a multitude of applications. FPGAs are considered affordable, but design cost, high reconfiguration delay and power consumption are all prohibitive. In this paper, we propose a novel ASIC based flexible MPSoC architecture, which can execute separate tasks in parallel, and it can be configured to execute single task with wide data widths or execute multiple tasks with varying data widths. The architecture presented, called Dynamically Reconfigurable MPSoC Architecture (DRMA), can be rapidly reconfigured through instructions. We present applications as case studies to showcase the flexibility and efficacy of DRMA. Results show for an additional area overhead of about 5%, the system is capable of working as four 32-bit processors, a single 128 bit processor or as a pipelined processing system.",
            "authors": [
                "Lawrance Zhang",
                "Jude Angelo Ambrose",
                "Jorgen Peddersen",
                "Sri Parameswaran",
                "Roshan Ragel",
                "Swarnalatha Radhakrishnan",
                "Kewal K. Saluja"
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        {
            "title": "Exploring multilevel cache hierarchies in application specific mpsocs",
            "venue": "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems",
            "year": "2015",
            "abstract": "Multiprocessor systems make use of multilevel cache hierarchies to improve overall memory access speed. Embedded systems typically use configurable processors, where the caches in the system can be customized for a given application or a set of applications. Finding the optimal or a near-optimal set size, block size, and associativity of each of the caches in a multilevel cache hierarchy is a challenging task due to the presence of billions or even trillions of design points. This paper presents an iterative exploration method to find suitable configurations for all the caches in the hierarchy of an application specific multiprocessor system-on-chip, to improve memory access speed. We propose an algorithm and combine it with the use of specialized hardware for parallel cache simulation to enable multiple back-and-forth iterations through the cache levels. In every iteration, our algorithm explores selected portions of the entire design space to quickly converge upon the final design point. We demonstrate our methodology on two- and three-level cache hierarchies with private and shared caches in a quad-core system, respectively, consisting of 5.4 billion and 10.4 trillion design points. Our method was able to find design points with up to 18.9% lower average memory access time while reducing total cache size by up to 74.15%, compared to a state-of-the-art noniterative method. The number of design points explored was 4\u00c3\u0097 higher in our method, which is still a mere 3.6 \u00c3\u0097 10 -5 % of the entire design space, and took 6.08 h.",
            "authors": [
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                "Haris Javaid",
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        {
            "title": "Exploring multilevel cache hierarchies in application specific mpsocs",
            "venue": "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems",
            "year": "2015",
            "abstract": "Multiprocessor systems make use of multilevel cache hierarchies to improve overall memory access speed. Embedded systems typically use configurable processors, where the caches in the system can be customized for a given application or a set of applications. Finding the optimal or a near-optimal set size, block size, and associativity of each of the caches in a multilevel cache hierarchy is a challenging task due to the presence of billions or even trillions of design points. This paper presents an iterative exploration method to find suitable configurations for all the caches in the hierarchy of an application specific multiprocessor system-on-chip, to improve memory access speed. We propose an algorithm and combine it with the use of specialized hardware for parallel cache simulation to enable multiple back-and-forth iterations through the cache levels. In every iteration, our algorithm explores selected portions of the entire design space to quickly converge upon the final design point. We demonstrate our methodology on two- and three-level cache hierarchies with private and shared caches in a quad-core system, respectively, consisting of 5.4 billion and 10.4 trillion design points. Our method was able to find design points with up to 18.9% lower average memory access time while reducing total cache size by up to 74.15%, compared to a state-of-the-art noniterative method. The number of design points explored was 4\u00c3\u0097 higher in our method, which is still a mere 3.6 \u00c3\u0097 10 -5 % of the entire design space, and took 6.08 h.",
            "authors": [
                "Isuru Nawinne",
                "Haris Javaid",
                "Roshan Ragel",
                "Swarnalatha Radhakrishnan",
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            "doi": "https://doi.org/10.1109/TCAD.2015.2445736",
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        {
            "title": "Power-Aware High-Level Synthesis Flow for Mapping FPGA Designs",
            "venue": "2019 Moratuwa Engineering Research Conference (MERCon)",
            "year": "2019",
            "abstract": "Present Field Programmable Gate Array (FPGA) manufacturers incorporate multi-millions of logic resources which enables hardware designers to design applications extending to large scales. However, handling such applications by existing FPGA Computer Aided Design (CAD) flow requires more improvement in terms of area, performance and power efficiency considerations. The current CAD flow requires the input design to be in Register Transfer Level (RTL). RTL input designs limit the design productivity only to hardware experts in performing analysis for various optimisations. Optimising RTL designs manually are increasingly hard. High-Level Synthesis (HLS) is an approach capable of increasing the design productivity of hardware applications compared to commonly used Hardware Description Languages (HDLs) and is known to be an intelligent approach for performing optimisations at a higher level of abstraction. In this paper, an approach that follows the HLS flow to cater to the mapping of FPGA applications in a power efficient manner using a communication-aware partitioning strategy is proposed. From experiments, it was possible to achieve an average reduction of 8.39% routing thermal power and 3.34% total power using the proposed approach.",
            "authors": [
                "Udaree Kanewala",
                "Kesara Gamlath",
                "Hasindu Ramanayake",
                "Kalindu Herath",
                "Isuru Nawinne",
                "Roshan Ragel"
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                {
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                {
                    "name": "Isuru Nawinne",
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                    "name": "Roshan Ragel",
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            "doi": "https://doi.org/10.1109/MERCon.2019.8818883",
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                "Accelerated and High-Performance Computing (FPGA / GPU)",
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            "tags": [
                "Field programmable gate arrays",
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        {
            "title": "An ensemble learning approach for electrocardiogram sensor based human emotion recognition",
            "venue": "MDPI Sensors",
            "year": "2019",
            "abstract": "Recently, researchers in the area of biosensor based human emotion recognition have used different types of machine learning models for recognizing human emotions. However, most of them still lack the ability to recognize human emotions with higher classification accuracy incorporating a limited number of bio-sensors. In the domain of machine learning, ensemble learning methods have been successfully applied to solve different types of real-world machine learning problems which require improved classification accuracies. Emphasising on that, this research suggests an ensemble learning approach for developing a machine learning model that can recognize four major human emotions namely: anger; sadness; joy; and pleasure incorporating electrocardiogram (ECG) signals. As feature extraction methods, this analysis combines four ECG signal based techniques, namely: heart rate variability; empirical mode decomposition; with-in beat analysis; and frequency spectrum analysis. The first three feature extraction methods are well-known ECG based feature extraction techniques mentioned in the literature, and the fourth technique is a novel method proposed in this study. The machine learning procedure of this investigation evaluates the performance of a set of well-known ensemble learners for emotion classification and further improves the classification results using feature selection as a prior step to ensemble model training. Compared to the best performing single biosensor based model in the literature, the developed ensemble learner has the accuracy gain of 10.77%. Furthermore, the developed model outperforms most of the multiple biosensor based emotion recognition models with a significantly higher classification accuracy gain.",
            "authors": [
                "Theekshana Dissanayake",
                "Yasitha Rajapaksha",
                "Roshan Ragel",
                "Isuru Nawinne"
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            "author_info": [
                {
                    "name": "Theekshana Dissanayake",
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                {
                    "name": "Yasitha Rajapaksha",
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                {
                    "name": "Roshan Ragel",
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            "doi": "https://doi.org/10.3390/s19204495",
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        {
            "title": "A Programming Framework for Robot Swarms",
            "venue": "2020 Moratuwa Engineering Research Conference (MERCon)",
            "year": "2020",
            "abstract": "Swarm robotics is a well-evolved research area over the past couple of decades. In this paper, we introduce a framework for programming swarm robots in a novel approach based on behaviour categorization, pheromone communication, and state representation. The framework is packaged with a set of well defined and tested behaviours that are structured based on the level of interactions between robots. These behaviours can be combined and integrated into the user code when implementing new behaviours. Robots function in a user-defined state and perform actions attributed to that state. We have used a behaviour- based bottom-up design approach for designing these behaviours which eventually alleviate the debugging and implementation process. The efficacy of our work is validated using results obtained from a custom-built simulation platform. These results include tests involving an random movement behaviour, an object finding behaviour, and implementation of an aggregation behaviour.",
            "authors": [
                "Mahendra Dassanayaka",
                "Tharuka Bandara",
                "Nadun Adikari",
                "Isuru Nawinne",
                "Roshan Ragel"
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            "author_info": [
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                    "name": "Mahendra Dassanayaka",
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                {
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        {
            "title": "Mixed-Reality Based Multi-Agent Robotics Framework for Artificial Swarm Intelligence Experiments",
            "venue": "IEEE Access",
            "year": "2023",
            "abstract": "",
            "authors": [
                "Dilshani Karunarathna",
                "Nuwan Jaliyagoda",
                "Ganindu Jayalath",
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                "Roshan Ragel",
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            "title": "Simultaneous Localization and Mapping with Cost Effective Sensors",
            "venue": "2025 International Research Conference on Smart Computing and Systems Engineering (SCSE)",
            "year": "2025",
            "abstract": "This paper explores the fascinating field of swarm robotics, where multiple robots collaborate to achieve tasks in a decentralized and distributed manner. The focus here is on the exploratory behavior of swarm robotics, including aggregation, dispersion, and collective movement. The system is represented as an occupancy grid problem and heuristic-based algorithms are used as optimized solutions. The decentralized approach within those methods makes them easier to idealize with current swarm robotic applications. Furthermore, these algorithms can be seamlessly integrated with other current frontier-based exploration techniques to enhance robot cooperation. All these proposed methods have been tested in different simulation environments, which mimic real world scenarios.",
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            "project": "https://projects.ce.pdn.ac.lk/4yp/e18/PeraSwarm-Simultaneous-Localization-and-Mapping-in-Mixed-Reality-Environment/",
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    "Machine Learning and Data Mining": [
        {
            "title": "Chronic kidney disease prediction using machine learning methods",
            "venue": "2020 Moratuwa Engineering Research Conference (MERCon) - IEEE",
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            "venue": "Sri Lanka Journal of Medicine",
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            "abstract": "Dengue outbreaks pose a significant public health challenge in tropical and subtropical regions globally, necessitating effective predictive models for early detection and intervention. This study examines the complex nature of the disease by analyzing weather parameters such as temperature, wind speed, precipitation, and humidity. Through machine learning techniques, we successfully forecasted dengue outbreaks in nine districts in Sri Lanka and identified similar weather and dengue patterns in districts such as Gampaha, Colombo, Kandy and Kurunegala. These findings are important for developing an early warning system, optimizing public health measures, and efficiently allocating resources to minimize the negative impact on communities. Furthermore, the model offers valuable insights for epidemiological research on dengue spread and control.",
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            "title": "Security weaknesses of WEP protocol IEEE 802.11b and enhancing the security with dynamic keys",
            "venue": "2009 IEEE Toronto International Conference Science and Technology for Humanity (TIC-STH)",
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            "abstract": "In wireless data communication, security has become an important measure. In this paper, we reveal vulnerabilities and weaknesses of WEP protocol which is used in IEEE 802.11b. The major issue of WEP protocol is the lack of a proper key management technique. We propose a method to overcome above by introducing a dynamic key for authentication and data transmission on per data frame basis.",
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            "title": "Security weaknesses of WEP protocol IEEE 802.11b and enhancing the security with dynamic keys",
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        {
            "title": "On implementing a client-server setting to prevent the Browser Reconnaissance and Exfiltration via Adaptive Compression of Hypertext (BREACH) attacks",
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            "abstract": "Compression is desirable for network applications as it saves bandwidth. Differently, when data is compressed before being encrypted, the amount of compression leaks information about the amount of redundancy in the plaintext. This side channel has led to the \u00e2\u0080\u009cBrowser Reconnaissance and Exfiltration via Adaptive Compression of Hypertext (BREACH)\u00e2\u0080\u009d attack on web traffic protected by the TLS protocol. The general guidance to prevent this attack is to disable HTTP compression, preserving confidentiality but sacrificing bandwidth. As a more sophisticated countermeasure, fixed-dictionary compression was introduced in 2015 enabling compression while protecting high-value secrets, such as cookies, from attacks. The fixed-dictionary compression method is a cryptographically sound countermeasure against the BREACH attack, since it is proven secure in a suitable security model. In this project, we integrate the fixed-dictionary compression method as a countermeasure for BREACH attack, for real-world client-server setting. Further, we measure the performance of the fixed-dictionary compression algorithm against the DEFLATE compression algorithm. The results evident that, it is possible to save some amount of bandwidth, with reasonable compression/decompression time compared to DEFLATE operations. The countermeasure is easy to implement and deploy, hence, this would be a possible direction to mitigate the BREACH attack efficiently, rather than stripping off the HTTP compression entirely.",
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            "title": "Leakage-resilient storage scheme for cryptographic applications",
            "venue": "2016 IEEE International Conference on Information and Automation for Sustainability (ICIAfS)",
            "year": "2016",
            "abstract": "Since the side-channel attacks arise as a huge threat for cryptographic schemes than previously realized, it is necessary to implement proven-secure leakage-resilient cryptographic schemes and use them for real-world purposes. In this work our effort is to implement two leakage-resilient cryptographic schemes, a leakage-resilient storage scheme and a refreshing protocol, which have been proven-secure and accepted by the cryptographic community since 2011 (ASIACRYPT 2011). Our aim is to open up the direction for implementing the useful leakage-resilient cryptographic schemes for future usage.",
            "authors": [
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        {
            "title": "Generic construction of an  eCK -secure key exchange protocol in the standard model",
            "venue": "International Journal of Information Security",
            "year": "2017",
            "abstract": "",
            "authors": [
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            "title": "Leakage-resilient non-interactive key exchange in the continuous-memory leakage setting",
            "venue": "International Conference on Provable Security",
            "year": "2017",
            "abstract": "Recently, Chakraborty et al. (Cryptoeprint:2017:441) showed a novel approach of constructing several leakage-resilient cryptographic primitives by introducing a new primitive called leakage-resilient non-interactive key exchange (LR-NIKE). Their construction of LR-NIKE was only in the bounded-memory leakage model, and they left open the construction of LR-NIKE in continuous-memory leakage model. In this paper we address that open problem. Moreover, we extend the continuous-memory leakage model by addressing more realistic after-the-fact leakage. The main ingredients of our construction are a leakage-resilient storage scheme and a refreshing protocol (Dziembowski and Faust, Asiacrypt 2011) and a (standard) chameleon hash function (CHF), equipped with an additional property of oblivious sampling, which we introduce. We observe that the present constructions of CHF already satisfies our new notion. Further, our protocol can be used as a building block to construct leakage-resilient public-key encryption schemes, interactive key exchange and low-latency key exchange protocols in the continuous-memory leakage model, following the approach of Chakraborty et al. (Cryptoeprint:2017:441).",
            "authors": [
                "Suvradip Chakraborty",
                "Janaka Alawatugoda",
                "C Pandu Rangan"
            ],
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                {
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                {
                    "name": "C Pandu Rangan",
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            ],
            "doi": "https://doi.org/10.1007/978-3-319-68637-0_10",
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            "researchgroups": [
                "Secure and Reliable Computing (Formal Verification / Cryptography / Blockchain)"
            ],
            "funding": "",
            "tags": [
                "Leakage-resilient",
                "Key exchange protocols",
                "After-the-fact leakage",
                "Continuous-memory leakage"
            ],
            "api_url": "https://api.ce.pdn.ac.lk/publications/v1/10.1007/978-3-319-68637-0_10/",
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        },
        {
            "title": "On the leakage-resilient key exchange",
            "venue": "Journal of Mathematical Cryptology",
            "year": "2017",
            "abstract": "Typically, secure channels are constructed from an authenticated key exchange (AKE) protocol, which authenticates the communicating parties based on long-term public keys and establishes secret session keys. In this paper we address the partial leakage of long-term secret keys of key exchange protocol participants due to various side-channel attacks. Security models for two-party authenticated key exchange protocols have been developed over time to provide security even when the adversary learns certain secret values. This paper combines and extends the advances of security modelling for AKE protocols addressing more granular partial leakage of long-term secrets of protocol participants. Further, we fix some flaws in security proofs of previous leakage-resilient key exchange protocols.",
            "authors": [
                "Janaka Alawatugoda"
            ],
            "author_info": [
                {
                    "name": "Janaka Alawatugoda",
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                    "type": "STAFF",
                    "id": "alawatugoda",
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            ],
            "doi": "https://doi.org/10.1515/jmc-2016-0003",
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            "preprint": "#",
            "pdf": "https://www.degruyter.com/document/doi/10.1515/jmc-2016-0003/pdf",
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            "researchgroups": [
                "Secure and Reliable Computing (Formal Verification / Cryptography / Blockchain)"
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            "tags": [
                "Key exchange protocols",
                "security models",
                "leakage-resilient cryptography"
            ],
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        },
        {
            "title": "Implementing a proven-secure and cost-effective countermeasure against the compression ratio info-leak mass exploitation (CRIME) attack",
            "venue": "2017 IEEE International Conference on Industrial and Information Systems (ICIIS)",
            "year": "2017",
            "abstract": "Header compression is desirable for network applications as it saves bandwidth and reduces latency. However, when data is compressed before being encrypted, the amount of compression leaks information about the amount of redundancy in the plaintext. In web requests, headers contain secret web cookies. Therefore, compression of headers before encryption will reveal the information about the secret web cookies. This side-channel has led to Compression Ratio Info-leak Made Easy (CRIME) attack on web traffic protected by the SSL/TLS protocols. In order to mitigate the CRIME attack, compression is completely disabled at the TLS/SSL layer, which in return increases the bandwidth consumption and latency. In a previous work (Financial Cryptography and Data Security 2015), two countermeasures are presented with formal security proofs, against compression side-channel attacks, namely (l)-separating secret cookies from user inputs and (2)-using a static compression dictionary. In this work we create a test environment to replicate the CRIME attack and verify the attack. Moreover, we implement a proven-secure countermeasure against the CRIME attack, in a real world client/server setup, following the aforementioned two countermeasures. Our implementation achieves better compression ratio (closer to the original TLS/SSL compression), and hence reduces the bandwidth usage and latency significantly (therefore cost-effective). To the best of our knowledge, this is the first proven-secure and cost-effective countermeasure implementation against the CRIME attack.",
            "authors": [
                "Jayamine Alupotha",
                "Sanduni Prasadi",
                "Janaka Alawatugoda",
                "Roshan Ragel",
                "Mohamed Fawsan"
            ],
            "author_info": [
                {
                    "name": "Jayamine Alupotha",
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                {
                    "name": "Sanduni Prasadi",
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                },
                {
                    "name": "Janaka Alawatugoda",
                    "profile": "https://people.ce.pdn.ac.lk/staff/academic/janaka-alawatugoda/",
                    "type": "STAFF",
                    "id": "alawatugoda",
                    "email": "alawatugoda@eng.pdn.ac.lk",
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                    "profile_url": "https://people.ce.pdn.ac.lk/staff/academic/janaka-alawatugoda/"
                },
                {
                    "name": "Roshan Ragel",
                    "profile": "https://people.ce.pdn.ac.lk/staff/academic/roshan-ragel/",
                    "type": "STAFF",
                    "id": "roshanr",
                    "email": "roshanr@eng.pdn.ac.lk",
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                {
                    "name": "Mohamed Fawsan",
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                    "email": "",
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            ],
            "doi": "https://doi.org/10.1109/ICIINFS.2017.8300359",
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            "preprint": "https://www.researchgate.net/profile/Roshan-Ragel/publication/323352314_Implementing_a_proven-secure_and_cost-effective_countermeasure_against_the_compression_ratio_info-leak_mass_exploitation_CRIME_attack/links/61c959beb8305f7c4b0421bc/Implementing-a-proven-secure-and-cost-effective-countermeasure-against-the-compression-ratio-info-leak-mass-exploitation-CRIME-attack.pdf",
            "pdf": "#",
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            "researchgroups": [
                "Secure and Reliable Computing (Formal Verification / Cryptography / Blockchain)"
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            "funding": "",
            "tags": [
                "Bandwidth",
                "Side-channel attacks",
                "Dictionaries",
                "Servers",
                "Data compression"
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            "api_url": "https://api.ce.pdn.ac.lk/publications/v1/10.1109/ICIINFS.2017.8300359/",
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        {
            "title": "Review on leakage resilient key exchange security models",
            "venue": "International Journal of Communication Networks and Information Security",
            "year": "2019",
            "abstract": "In leakage resilient cryptography, leakage resilient key exchange protocols are constructed to defend against leakage attacks. Then, the key exchange protocol is proved with leakage resilient security model to determine whether its security proof can provide the security properties it claimed or to find out any unexamined flaw during protocol building. It is an interesting work to review the meaningful security properties provided by these security models. This work review how a leakage resilient security model for a key exchange protocol has been evolved over years according to the increasing security requirement which covers a different range of attacks. The relationship on how an adversary capability in the leakage resilient security model can be related to real-world attack scenarios is studied. The analysis work for each leakage resilient security model here enables a better knowledge on how an adversary query addresses different leakage attacks setting, thereby understand the motive of design for a cryptographic primitive in the security model.",
            "authors": [
                "Clement Chan Zheng Wei",
                "Chuah Chai Wen",
                "Janaka Alawatugoda\\"
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                {
                    "name": "Clement Chan Zheng Wei",
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                {
                    "name": "Chuah Chai Wen",
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                    "type": "STAFF",
                    "id": "alawatugoda",
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                {
                    "name": "Janaka Alawatugoda\\",
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            "doi": "https://doi.org/10.17762/ijcnis.v11i1.3790",
            "is_dept_affiliated": true,
            "preprint": "https://www.researchgate.net/profile/Clement-Zheng-Wei/publication/332671720_Review_on_Leakage_Resilient_Key_Exchange_Security_Model/links/5cc2c6e1a6fdcc1d49af2c1a/Review-on-Leakage-Resilient-Key-Exchange-Security-Model.pdf",
            "pdf": "https://www.ijcnis.org/index.php/ijcnis/article/view/3790/705",
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            "researchgroups": [
                "Secure and Reliable Computing (Formal Verification / Cryptography / Blockchain)"
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            "tags": [
                "Leakage-resilient cryptography",
                "Key exchange protocol",
                "Security models",
                "Leakage attacks",
                "Side-channel attacks",
                "Leakage resilience"
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        },
        {
            "title": "New approach to practical leakage-resilient public-key cryptography",
            "venue": "Journal of Mathematical Cryptology",
            "year": "2020",
            "abstract": "We present a new approach to construct several leakage-resilient cryptographic primitives, including leakage-resilient public-key encryption (PKE) schemes, authenticated key exchange (AKE) protocols and low-latency key exchange (LLKE) protocols. To this end, we introduce a new primitive called leakage-resilient non-interactive key exchange (LR-NIKE) protocol. We introduce an appropriate security model for LR-NIKE protocols in the bounded memory leakage (BML) settings. We then show a secure construction of the LR-NIKE protocol in the BML setting that achieves an optimal leakage rate, i.e., 1 \u00e2\u0080\u0093 o(1). Our construction of LR-NIKE requires a minimal use of a leak-free hardware component. We argue that the use of such a leak-free hardware component seems to be unavoidable in any construction of an LR-NIKE protocol, even in the BML setting. Finally, we show how to construct the aforementioned leakage-resilient primitives from such an LR-NIKE protocol as summarized below. All these primitives also achieve the same (optimal) leakage rate as the underlying LR-NIKE protocol. We show how to construct a leakage-resilient (LR) IND-CCA-2-secure PKE scheme in the BML model generically from a bounded LR-NIKE (BLR-NIKE) protocol. Our construction of LR-IND-CCA-2 secure PKE differs significantly from the state-of-the-art constructions of these primitives, which mainly use hash proof techniques to achieve leakage resilience. Moreover, our transformation preserves the leakage-rate of the underlying BLR-NIKE protocol. We introduce a new leakage model for AKE protocols, in the BML setting, and present a leakage-resilient AKE protocol construction from the LR-NIKE protocol. We introduce the first-ever leakage model for LLKE protocols in the BML setting and the first construction of such a leakage-resilient LLKE from the LR-NIKE protocol.",
            "authors": [
                "Suvradip Chakraborty",
                "Janaka Alawatugoda",
                "Chandrasekaran Pandu Rangan"
            ],
            "author_info": [
                {
                    "name": "Suvradip Chakraborty",
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                },
                {
                    "name": "Janaka Alawatugoda",
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                {
                    "name": "Chandrasekaran Pandu Rangan",
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            ],
            "doi": "https://doi.org/10.1515/jmc-2019-0014",
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            "pdf": "https://www.degruyter.com/document/doi/10.1515/jmc-2019-0014/pdf",
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            "researchgroups": [
                "Secure and Reliable Computing (Formal Verification / Cryptography / Blockchain)"
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            "funding": "",
            "tags": [
                "Leakage-resilient cryptography",
                "public-key cryptography",
                "non-interactive key exchange",
                "authenticated key exchange",
                "low-latency key exchange"
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            "api_url": "https://api.ce.pdn.ac.lk/publications/v1/10.1515/jmc-2019-0014/",
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        },
        {
            "title": "Public-key encryption in the standard model against strong leakage adversary",
            "venue": "The Computer Journal",
            "year": "2020",
            "abstract": "Over the years, security against adaptively chosen-ciphertext attacks (CCA2) is considered as the strongest security definition for public-key encryption schemes. With the uprise of side-channel attacks, new security definitions are proposed, addressing leakage of secret keys together with the standard CCA2 definition. Among the new security definitions, security against continuous and after-the-fact leakage-resilient CCA2 can be considered as the strongest security definition, which is called as security against (continuous) adaptively chosen-ciphertext leakage attacks (continuous CCLA2). In this paper, we present a construction of a public-key encryption scheme, namely LR-PKE, which satisfies the aforementioned security definition. The security of our public-key encryption scheme is proven in the standard model, under decision BDH assumption. Thus, we emphasize that our public-key encryption scheme LR-PKE is (continuous) CCLA2-secure in the standard model. For our construction of LR-PKE, we have used a strong one-time signature scheme and a leakage-resilient refreshing protocol as underlying building blocks. The leakage bound is 0.15nlogp\u00e2\u0088\u00921 bits per leakage query, for a security parameter k and a statistical security parameter n\u00e2\u0081\u00a0, such that logp\u00e2\u0089\u00a5k and n is a function of k\u00e2\u0081\u00a0. It is possible to see that LR-PKE is efficient enough to be used for real-world usage.",
            "authors": [
                "Janaka Alawatugoda"
            ],
            "author_info": [
                {
                    "name": "Janaka Alawatugoda",
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            ],
            "doi": "https://doi.org/10.1093/comjnl/bxaa055",
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            "preprint": "https://research-repository.griffith.edu.au/bitstream/handle/10072/414338/Alawatugoda522794-Accepted.pdf?sequence=2",
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        {
            "title": "On power analysis attacks against hardware stream ciphers",
            "venue": "International Journal of Information and Computer Security",
            "year": "2022",
            "abstract": "Power analysis attacks are a type of attack which measures and analyses the power consumption of electronic circuits to extract secret information, particularly the secret encryption key. These attacks have become a huge threat for embedded systems, in which the security depends on the secret encryption key for the ciphers. Hence, many researchers try to find vulnerabilities of cryptosystems against power analysis attacks, so that they can develop countermeasures to ensure the security of such systems. In this paper, we review some of the recent power analysis attacks on modern hardware stream ciphers such as Trivium, Grain and MICKEY.",
            "authors": [
                "Rangana De Silva",
                "Iranga Navaratna",
                "Malitha Kumarasiri",
                "Janaka Alawatugoda",
                "Chuah Chai Wen"
            ],
            "author_info": [
                {
                    "name": "Rangana De Silva",
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                {
                    "name": "Iranga Navaratna",
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                {
                    "name": "Malitha Kumarasiri",
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                },
                {
                    "name": "Janaka Alawatugoda",
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                    "id": "alawatugoda",
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                },
                {
                    "name": "Chuah Chai Wen",
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                    "id": "",
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                    "profile_image": "#",
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            ],
            "doi": "https://doi.org/10.1504/ijics.2022.121289",
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            "project": "https://projects.ce.pdn.ac.lk/4yp/e13/power-analysis-attack-on-trivium-stream-cipher",
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            "researchgroups": [
                "Secure and Reliable Computing (Formal Verification / Cryptography / Blockchain)"
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            "funding": "",
            "tags": [
                "differential power analysis",
                "correlation power analysis",
                "simple power analysis",
                "power analysis attack",
                "stream cipher",
                "Trivium",
                "Grain",
                "MICKEY"
            ],
            "api_url": "https://api.ce.pdn.ac.lk/publications/v1/10.1504/ijics.2022.121289/",
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        },
        {
            "title": "Standard model leakage-resilient authenticated key exchange using inner-product extractors",
            "venue": "Designs, Codes and Cryptography",
            "year": "2022",
            "abstract": "With the development of side-channel attacks, a necessity arises to invent authenticated key exchange protocols in a leakage-resilient manner. Constructing authenticated key exchange protocols using existing cryptographic schemes is an effective method, as such construction can be instantiated with any appropriate scheme in a way that the formal security argument remains valid. In parallel, constructing authenticated key exchange protocols that are proven to be secure in the standard model is more preferred as they rely on real-world assumptions. In this paper, we present a Diffie\u00e2\u0080\u0093Hellman-style construction of a leakage-resilient authenticated key exchange protocol, that can be instantiated with any CCLA2-secure public-key encryption scheme and a function from the pseudo-random function family. Our protocol is proven to be secure in the standard model assuming the hardness of the decisional Diffie\u00e2\u0080\u0093Hellman problem. Furthermore, it is resilient to continuous partial leakage of long-term secret keys, that happens even after the session key is established, while satisfying the security features defined by the eCK security model.",
            "authors": [
                "Janaka Alawatugoda",
                "Tatsuaki Okamoto"
            ],
            "author_info": [
                {
                    "name": "Janaka Alawatugoda",
                    "profile": "https://people.ce.pdn.ac.lk/staff/academic/janaka-alawatugoda/",
                    "type": "STAFF",
                    "id": "alawatugoda",
                    "email": "alawatugoda@eng.pdn.ac.lk",
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                },
                {
                    "name": "Tatsuaki Okamoto",
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            ],
            "doi": "https://doi.org/10.1007/s10623-022-01028-0",
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            "preprint": "https://eprint.iacr.org/2021/861.pdf",
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            "researchgroups": [
                "Secure and Reliable Computing (Formal Verification / Cryptography / Blockchain)"
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            "tags": [
                "Leakage-resilient cryptography",
                "Authenticated key exchange",
                "eCK model",
                "CAFL-eCK model",
                "Standard model"
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            "title": "Internet of things (IoT) for smart agriculture: Assembling and assessment of a low-cost IoT system for polytunnels",
            "venue": "PLOS One",
            "year": "2023",
            "abstract": "Internet of things (IoT) applications in smart agricultural systems vary from monitoring climate conditions, automating irrigation systems, greenhouse automation, crop monitoring and management, and crop prediction, up to end-to-end autonomous farm management systems. One of the main challenges to the advancement of IoT systems for the agricultural domain is the lack of training data under operational environmental conditions. Most of the current designs are based on simulations and artificially generated data. Therefore, the essential first step is studying and understanding the finely tuned and highly sensitive mechanism plants have developed to sense, respond, and adapt to changes in their environment, and their behavior under field and controlled systems. Therefore, this study was designed to achieve two specific objectives; to develop low-cost IoT components from basic building blocks, and to study the performance of the developed systems, and generate real-time experimental data, with and without plants. Low-cost IoT devices developed locally were used to convert existing basic polytunnels to semi-controlled and monitoring-only polytunnels. Their performances were analyzed and compared with each other based on several matrices while maintaining the planted tomato variety and agronomic practices similar. The developed system performed as expected suggesting the possibility of commercial applications and research purposes.",
            "authors": [
                "Nuwan Jaliyagoda",
                "Sandali Lokuge",
                "P.M.P.C. Gunathilake",
                "K.S.P. Amaratunga",
                "W.A.P.Weerakkody",
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                    "name": "K.S.P. Amaratunga",
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            "codebase": "https://github.com/cepdnaclk/Smart-Agriculture-a-low-cost-IoT-system-for-polytunnels",
            "researchgroups": [
                "Smart and Intelligent Systems (IoT / AI / Wearable Computing)"
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            "funding": "The Early Career Fellowship of the Organization for Women in Science for Developing World (OWSD, Early Career Fellowship https://owsd.net/) funded this project \u00e2\u0080\u0093 the award agreement 4500406736 was awarded to Pradeepa C.G. Bandaranayake",
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                "IoT",
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        {
            "title": "Simultaneous Localization and Mapping with Cost Effective Sensors",
            "venue": "2025 International Research Conference on Smart Computing and Systems Engineering (SCSE)",
            "year": "2025",
            "abstract": "This paper explores the fascinating field of swarm robotics, where multiple robots collaborate to achieve tasks in a decentralized and distributed manner. The focus here is on the exploratory behavior of swarm robotics, including aggregation, dispersion, and collective movement. The system is represented as an occupancy grid problem and heuristic-based algorithms are used as optimized solutions. The decentralized approach within those methods makes them easier to idealize with current swarm robotic applications. Furthermore, these algorithms can be seamlessly integrated with other current frontier-based exploration techniques to enhance robot cooperation. All these proposed methods have been tested in different simulation environments, which mimic real world scenarios.",
            "authors": [
                "Dinuka Mudalige",
                "Nipun Dharmarathne",
                "Yojith Jayarathna",
                "Nuwan Jaliyagoda",
                "Akila Karunanayake",
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                "Isuru Nawinne"
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                {
                    "name": "Nuwan Jaliyagoda",
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                    "type": "STUDENT",
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                    "name": "Roshan Ragel",
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                    "type": "STAFF",
                    "id": "roshanr",
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                    "name": "Isuru Nawinne",
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                    "type": "STAFF",
                    "id": "isurunawinne",
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            "project": "https://projects.ce.pdn.ac.lk/4yp/e18/PeraSwarm-Simultaneous-Localization-and-Mapping-in-Mixed-Reality-Environment/",
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